Physics
- Volume Conservation, Dark Matter, and Dark Energy [PDF] - Revision 0.91 A quantum-cosmology and quantum-physics preprint.
Poetry
- Symmetry Emergent [PDF] A poem on the nature of spacetime, entanglement, cosmology, decoherence, causality, and consciousness.
Microarchitecture
Papers
- Ivy Bridge Server: A Converged Design (IEEE Micro, 2015)
- FastMP: A Multi-core Simulation Methodology (IEEE, 2006)
Intel Patents
- Techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access by a system (US Patent App. 18/821,878)
- Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement (US Patent App. 19/008,948)
- Function as a service (FaaS) system enhancements (US Patent 11,922,220)
- Multiple dies hardware processors and methods (US Patent 11,899,615)
- System, apparatus and method for adaptive interconnect routing (US Patent 11,256,657)
- Cache line demote infrastructure for multi-processor pipelines (US Patent App. 17/086,243)
- System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms (US Patent 10,936,490)
- Link affinitization to reduce transfer latency (US Patent App. 16/894,402)
- Scalably mechanism to implement an instruction that monitors for writes to an address (US Patent 10,705,961)
- Buffered interconnect for highly scalable on-die fabric (US Patent App. 16/227,364)
- Virtual retry queue (US Patent 10,338,974)
- Value of forward state by increasing local caching agent forwarding (US Patent 10,204,049)
- Two level memory full line writes (US Patent 10,140,213)
- Cache allocation with code and data prioritization (US Patent 10,089,229)
- Optimized caching agent with integrated directory cache (US Patent App. 15/396,174)
- Method, apparatus and system for modular on-die coherent interconnect for packetized communication (US Patent 9,921,989)
- Method, apparatus and system for optimizing cache memory transaction handling in a processor (US Patent 9,606,925)
- Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory (US Patent 9,418,009)
- Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline (US Patent 9,207,753)
- Deadlock prevention in a processor (US Patent App. 14/142,137)
- Cache coherency apparatus and method minimizing memory writeback operations (US Patent App. 14/136,131)
- Mechanism to improve input/output write bandwidth in scalable systems utilizing directory based coherecy (US Patent App. 13/835,862)
- Method and apparatus for processing a predicated instruction using limited predicate slip (US Patent 6,883,089)